Testing of VSLI designs becomes more common with the growth of the complexity of such designs. Testing should be very accurate to reduce the number of non-detected faults. Testing should also be fast and inexpensive in terms of hardware and software overhead. An especially important task is the testing of memories. To reduce the size of a memory, gates and wires are typically placed very densely on a semiconductor wafer. Dense placement often results in a significantly higher ratio of faults (i.e., up to 4 times higher) in these areas. Fortunately, memories are very regular structures, so testing can be done on-chip, based on data sequences generated by relatively small processors. Such a processor can, for example, produce necessary data and address sequences (like well-known march test sequences), check the output signals of the memory and produce error reports and/or reconfiguration information to be used in self-repair mode.
If a design contains a single memory, the above-described solution works well. The controller is typically small enough (if compared with memory size), and can be placed near memory I/O ports (i.e., interconnection wiring and timing issues are not critical). However, if a number of memories are implemented on the same chip, and the memories have different sizes and configurations, testing becomes more complicated. Individual controllers can be implemented for each memory—but will potentially require a large overhead in gate count. Also, one controller could possibly be used for multiple memories—but at the expense of being very accurate in the synchronization of such an engine, and in the complexity of data interchange between controller and memories.
It would be desirable to implement a system and/or method with low gate complexity, moderate wiring and high flexibility that may uniformly interconnect memories of different sizes and types without limitations on the mutual placement of memories under test.